XR19L220_07 Datasheet, PDF (16/43 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L220
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
2.17.3 Power-Save Feature
This mode is in addition to the sleep mode and in this mode, the core logic of the L220 is isolated from the CPU
interface. If the address lines, data bus lines, IOW#, IOR# and CS# remain steady when the L220 is in full
sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical
Characteristics on page 32. However, if the input lines are floating or are toggling while the L220 is in sleep
mode, the current can be up to 100 times more. If not using the Power-Save feature, an external buffer would
be required to keep the address and data bus lines from toggling or floating to achieve the low current. But if
the Power-Save feature is enabled (PwrSave pin connected to VCC), this will eliminate the need for an
external buffer by internally isolating the address, data and control signals from other bus activities that could
cause wasteful power drain (see Figure 1). The L220 enters Power-Save mode when this pin is connected to
VCC, and the UART portion of the L220 is already in sleep mode.
Since Power-Save mode isolates the address, data and control signals, the device will wake-up only by:
■ a receive data start bit transition, or
■ a change of logic state on any of the modem or general purpose serial inputs: i.e., any of the MSR bits 0-
3 shows a ’1’
The L220 will return to the Power-Save mode automatically after a read to the MSR (to reset the modem
inputs) and all interrupting conditions have been serviced and cleared. The L220 will stay in the Power-Save
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the Power-Save pin is connected to
GND.
If the L220 is awakened by any one of the above conditions, it issues an interrupt as soon as the oscillator
circuit is up and running and the device is ready to transmit/receive. This interrupt has the same encoding (bit-
0 of ISR register = 1) as "no interrupt pending" and will clear when the ISR register is read. This will show up in
the ISR register only if no other interrupts are enabled.
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