XR19L220_07 Datasheet, PDF (14/43 Pages) Exar Corporation – SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER

XR19L220
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.1
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L220 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L220 sends the
Xoff character(s) two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level. To clear this condition, the L220 will transmit the
programmed Xon character(s) as soon as receive FIFO is less than one trigger level below the programmed
trigger level (see Table 8). The table below describes this.
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL INT PIN ACTIVATION
1
1
4
4
8
8
14
14
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
1*
4*
8*
14*
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
0
1
4
8
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.16 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L220 compares each incoming receive character with the programmed Xoff-2 data. If a match exists, the
received data will be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special
character. Although the Internal Register Table shows Xon, Xoff Registers with eight bits of character
information, the actual number of bits is dependent on the programmed word length. Line Control Register
(LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length
selected by LCR bits 0-1 also determines the number of bits that will be used for the special character
comparison. Bit-0 in the Xon, Xoff Registers corresponds with the LSB bit for the receive character.
2.17 Sleep Modes and Power-Save Feature with Wake-Up Interrupt
There are three levels of power management integrated in the L220. The device is low power with low
operational and standby supply currents. In the Partial Sleep mode, the internal oscillator of the UART or
charge pump of the RS-232 transceiver is turned off to reduce the power consumption. In the Full Sleep mode,
both the oscillator and the charge pump are turned off. The Power-save mode provides additional power
saving by isolating the UART address, data and control signals during Sleep mode to minimize the power
consumption.
2.17.1 Partial Sleep Mode
There are two different partial sleep modes. In the first mode, the UART is in sleep mode and the charge pump
is active. In the other mode, the UART is still active but the charge pump is turned off.
2.17.1.1 UART in sleep mode, RS-232 transceiver active
If the ACP pin is LOW, then the charge pump for the RS-232 transceiver will always be active. But the UART
portion in the L220 can still enter sleep mode if all of these conditions are satisfied:
■ no interrupts pending (ISR bit-0 = 1)
■ the 16-bit divisor programmed in DLM and DLL registers is a non-zero value
■ sleep mode is enabled (IER bit-4 = 1)
■ modem inputs are not toggling (MSR bits 0-3 = 0)
■ RXD input pin is idling LOW
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