XR16L2752 Datasheet, PDF (9/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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REV. 1.2.1
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
2.9 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 18
through 23.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485
Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INTA/B Pin
NO
LOW = a byte in THR
LOW = FIFO above trigger level
HIGH = THR empty
HIGH = FIFO below trigger level or FIFO empty
INTA/B Pin
YES
LOW = a byte in THR
LOW = FIFO above trigger level
HIGH = transmitter empty HIGH = FIFO below trigger level or transmitter empty
INTA/B Pin
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
2.10 Crystal Oscillator or External Clock Input
The 2752 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
R2
(Optional)
500 KΩ − 1 MΩ
C1
22-47 pF
Y1
1.8432 MHz
to
24 MHz
C2
22-47 pF
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