XR16L2752 Datasheet, PDF (49/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

xr
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
XR16L2752
REV. 1.2.1
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 23
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 24
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 25
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.7 ALTERNATE FUNCTION REGISTER (AFR) - READ/WRITE ....................................................................... 29
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 29
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 30
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 31
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 32
4.12 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 32
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 32
TABLE 13: RTS HYSTERESIS LEVELS ............................................................................................................................................. 33
4.13 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 33
4.14 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 34
4.15 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 34
4.16 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 34
4.17 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY ................................................................................. 34
4.18 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY .................................................................... 34
4.19 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 34
TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 36
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 37
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 38
ABSOLUTE MAXIMUM RATINGS .................................................................................. 39
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 39
ELECTRICAL CHARACTERISTICS................................................................................ 39
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 39
AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 40
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25-5.5V, ................ 40
70 pF load where applicable ..................................................................................................................................... 40
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 41
FIGURE 16. DATA BUS READ TIMING .............................................................................................................................................. 42
FIGURE 17. DATA BUS WRITE TIMING ............................................................................................................................................ 42
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 43
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 43
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 44
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 44
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 45
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 45
PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 46
REVISION HISTORY ...................................................................................................................................... 47
TABLE OF CONTENTS ............................................................................................................ I
II