XR16L2752 Datasheet, PDF (21/49 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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REV. 1.2.1
XR16L2752
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/ Modem RX Line TX
RX
CTS Int. RTS Int.
Enable Enable
Xoff Int.
Enable
Sleep
Mode
Enable
Stat. Stat. Empty Data
Int.
Int.
Int
Int.
Enable Enable Enable Enable
0 1 0 ISR RD FIFOs FIFOs
0/
0/
INT INT INT INT _{LCR[7] = 0}
Enabled Enabled
Source Source Source Source
INT
INT _{Bit-3 Bit-2 Bit-1 Bit-0}
Source Source
Bit-5 Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
DMA TX
RX FIFOs
Trigger Trigger
Mode FIFO FIFO Enable
TXFIFO TXFIFO _{Enable Reset Reset}
Trigger Trigger
011
100
LCR RD/WR Divisor Set TX Set Par- Even Parity Stop Word Word
Enable Break
ity
Parity Enable Bits Length Length
Bit-1 Bit-0
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal OP2# Rsrvd RTS# DTR#
Lopback Output _(OP1#) Output Output
Enable Control
Control Control
101
110
111
111
LSR RD RX FIFO THR & THR
Global TSR Empty
Error Empty
MSR RD
CD#
Input
SPR RD/WR Bit-7
RI#
Input
Bit-6
DSR#
Input
Bit-5
EMSR WR
16X
Sam-
pling
Rate
Mode
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
RTS
Hyst.
bit-3
RX
Break
RX
Fram-
ing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
LCR ≠ 0xBF
CTS# Delta Delta Delta Delta
Input CD# RI# DSR# CTS#
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR ≠ 0xBF
FCTR bit-6=0
Auto
RTS
Hyst.
bit-2
Auto
RS485
Output
Inver-
sion
Rsrvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR ≠ 0xBF
FCTR bit-6=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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