XR16L2450 Datasheet, PDF (9/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

xr
REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x
MCR Bit-7=0
Clock (Decimal) Clock (HEX)
400
2304
900
2400
384
180
4800
192
C0
9600
96
60
19.2k
48
30
38.4k
24
18
76.8k
12
0C
153.6k
6
06
230.4k
4
04
460.8k
2
02
921.6k
1
01
DLM PROGRAM
VALUE (HEX)
09
01
00
00
00
00
00
00
00
00
00
DLL PROGRAM
VALUE (HEX)
00
80
C0
60
30
18
0C
06
04
02
01
DATA RATE
ERROR (%)
0
0
0
0
0
0
0
0
0
0
0
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 1 byte FIFO or Transmit
Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods.
The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled,
and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5
and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 5. TRANSMITTER OPERATION
Data
Byte
Transmit
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
9