XR16L2450 Datasheet, PDF (15/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

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REV. 1.1.0
XR16L2450
2.25V TO 5.5V DUART
4.4.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by data byte received in RHR.
• TXRDY is by THR empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data out of RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
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TABLE 6: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL
ISR REGISTER STATUS BITS
BIT-3 BIT-2 BIT-1
BIT-0
SOURCE OF INTERRUPT
1
0
1
1
0 LSR (Receiver Line Status Register)
2
0
1
0
0 RXRDY (Received Data Ready)
3
0
0
1
0 TXRDY (Transmit Ready)
4
0
0
0
0 MSR (Modem Status Register)
-
0
0
0
1 None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 6).
ISR[7:4]: Reserved
4.5 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
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