XR16L2450 Datasheet, PDF (13/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

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REV. 1.1.0
.
XR16L2450
2.25V TO 5.5V DUART
TABLE 5: INTERNAL REGISTERS DESCRIPTION
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
COMMENT
16C450 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
000
001
THR WR
IER RD/WR
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3 Bit-2 Bit-1 Bit-0
Modem RX Line TX
RX
Stat. Stat. Empty Data
Int.
Int.
Int
Int.
Enable Enable Enable Enable
LCR[7] = 0
0 1 0 ISR RD
0
0
0
0
INT INT INT INT
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
011
LCR RD/WR Divisor Set TX Set Par- Even Parity Stop Word Word
Enable Break
ity
Parity Enable Bits Length Length
Bit-1 Bit-0
1 0 0 MCR RD/WR 0
0
0 Internal OP2#/ Rsrvd RTS# DTR#
Loop- INT _(OP1#) Output Output
back Output
Control Control
Enable Enable
1 0 1 LSR RD
0
THR & THR
RX
RX
RX
RX
RX
TSR Empty Break Fram- Parity Over- Data
Empty
ing Error run Ready
Error
Error
1 1 0 MSR RD
CD#
Input
RI#
Input
DSR#
Input
CTS# Delta Delta Delta Delta
Input CD# RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
000
001
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
0 0 0 DREV RD
0 0 1 DVID RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2
0
Bit-1
1
Bit-0
0
LCR[7]=1
DLL=0x00
DLM=0x00
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 10.
4.2 Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 9.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
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