XR16L2450 Datasheet, PDF(6/30 Page) Exar Corporation

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XR16L2450 Datasheet, PDF (6/30 Pages) Exar Corporation – 2.25V TO 5.5V DUART

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XR16L2450

2.25V TO 5.5V DUART

REV. 1.1.0

1.0 PRODUCT DESCRIPTION

The XR16L2450 (L2450) integrates the functions of 2 16C450 Universal Asynchrounous Receiver and

Transmitter (UART). Each UART is independently controlled having its own set of device configuration

registers. The L2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-

to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for

converting the serial data stream into parallel data that is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.

The L2450 represents such an integration with greatly enhanced features. The L2450 is fabricated with an

advanced CMOS process. The L2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a

crystal or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The L2450 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share

the same data bus for host operations. The data bus interconnections are shown in Figure 3.

FIGURE 3. XR16L2450 DATA BUS INTERCONNECTIONS

IOR#

IOW#

UART_CSA#

UART_CSB#

UART_INTA

UART_INTB

UART_RESET

IOR#

IOW#

CSA#

CSB#

INTA

INTB

VCC

UART

Channel A

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

OP2A#

UART

Channel B

TXB

RXB

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

RIB#

OP2B#

RESET

GND

VCC

RS-232 Serial Interface

2.2 5-Volt Tolerant Inputs

The L2450 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2450 is

operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial

transceiver that is operating at 5V.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 8). An active high pulse of at least 40 ns duration will be required to activate the reset function

in the device.

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