XRT86VX38A Datasheet, PDF (86/191 Pages) Exar Corporation – 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VX38A
8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. 1.0.0
BIT7
R/W
0
TABLE 71: RECEIVE SSM MATCH 1 REGISTER (RSSMMR1 0XN172H)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
Reserved
RSSMM1[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT0
R/W
0
BITS [7:4] - Reserved
BITS [3:0] - Receive SSM Match 1
These bits can be used to set an expected value to be compared to the actual receive SSM message. This register is
one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.
In addition, this register has a filter for consecutive message validation.
BIT7
R/W
0
TABLE 72: RECEIVE SSM MATCH 2 REGISTER (RSSMMR2 0XN173H)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
Reserved
RSSMM2[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT0
R/W
0
BITS [7:4] - Reserved
BITS [3:0] - Receive SSM Match 2
These bits can be used to set an expected value to be compared to the actual receive SSM message. This register is
one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.
In addition, this register has a filter for consecutive message validation.
BIT7
R/W
0
TABLE 73: RECEIVE SSM MATCH 3 REGISTER (RSSMMR3 0XN174H)
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
Reserved
RSSMM3[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
BIT0
R/W
0
BITS [7:4] - Reserved
BITS [3:0] - Receive SSM Match 3
These bits can be used to set an expected value to be compared to the actual receive SSM message. This register is
one of three possible expected values that can be set. Upon a match of this register, an independent alarm will be set.
In addition, this register has a filter for consecutive message validation.
83