XRT86VX38A Datasheet, PDF (106/191 Pages) Exar Corporation – 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VX38A
8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 99: PMON RECEIVE LINE CODE VIOLATION COUNTER LSB (RLCVCL)
REV. 1.0.0
HEX ADDRESS: 0XN901
BIT
FUNCTION
7 RLCVC[7]
6 RLCVC[6]
5 RLCVC[5]
4 RLCVC[4]
3 RLCVC[3]
2 RLCVC[2]
1 RLCVC[1]
0 RLCVC[0]
TYPE
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
DEFAULT
DESCRIPTION-OPERATION
0
Performance Monitor “Receive Line Code Violation” 16-Bit
Counter - Lower Byte:
0
These RESET-upon-READ bits, along with that within the PMON
0
Receive Line Code Violation Counter Register MSB combine to
reflect the cumulative number of instances that Line Code Violation
0
has been detected by the Receive E1 Framer block since the last
read of this register.
0
This register contains the Least Significant byte of this 16-bit of the
0
Line Code Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
0
counter first before reading the LSB counter in order to read
0
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
TABLE 100: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER MSB (RFAECU) HEX ADDRESS:
0XN902
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 RFAEC[15]
6 RFAEC[14]
5 RFAEC[13]
4 RFAEC[12]
3 RFAEC[11]
2 RFAEC[10]
1 RFAEC[9]
0 RFAEC[8]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
Performance Monitor “Receive Framing Alignment Error 16-Bit
Counter” - Upper Byte:
0
These RESET-upon-READ bits, along with that within the “PMON
0
Receive Framing Alignment Error Counter Register LSB” combine
to reflect the cumulative number of instances that the Receive
0
Framing Alignment errors has been detected by the Receive E1
Framer block since the last read of this register.
0
This register contains the Most Significant byte of this 16-bit of the
0
Receive Framing Alignment Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
0
counter first before reading the LSB counter in order to read
0
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
TABLE 101: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER LSB (RFAECL) HEX ADDRESS: 0XN903
BIT
FUNCTION
TYPE DEFAULT
DESCRIPTION-OPERATION
7 RFAEC[7]
6 RFAEC[6]
5 RFAEC[5]
4 RFAEC[4]
3 RFAEC[3]
2 RFAEC[2]
1 RFAEC[1]
0 RFAEC[0]
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
Performance Monitor “Receive Framing Alignment Error 16-Bit
Counter” - Lower Byte:
0
These RESET-upon-READ bits, along with that within the “PMON
0
Receive Framing Alignment Error Counter Register MSB” combine
to reflect the cumulative number of instances that the Receive
0
Framing Alignment errors has been detected by the Receive E1
Framer block since the last read of this register.
0
This register contains the Least Significant byte of this 16-bit of the
0
Receive Framing Alignment Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
0
counter first before reading the LSB counter in order to read
0
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
103