XRT86VX38A Datasheet, PDF (133/191 Pages) Exar Corporation – 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

XRT86VX38A
REV. 1.0.0
8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 127: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR)
HEX ADDRESS: 0XNB08
BIT
FUNCTION
1 RxSB_EMPT
0 RxSB_SLIP
TYPE
RUR/
WC
RUR/
WC
DEFAULT
DESCRIPTION-OPERATION
0
Receive Slip buffer Empty Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer
Empty interrupt has occurred since the last read of this register. The
Receive Slip Buffer Empty interrupt is declared when the receive slip
buffer is emptied. If the receive slip buffer is emptied and a READ opera-
tion occurs, then a full frame of data will be repeated, and this interrupt bit
will be set to ‘1’.
0 = Indicates that the Receive Slip Buffer Empty interrupt has not occurred
since the last read of this register.
1 = Indicates that the Receive Slip Buffer Empty interrupt has occurred
since the last read of this register.
0
Receive Slip Buffer Slips Interrupt Status
This Reset-Upon-Read bit indicates whether or not the Receive Slip Buffer
Slips interrupt has occurred since the last read of this register. The
Receive Slip Buffer Slips interrupt is declared when the receive slip buffer
is either filled or emptied. This interrupt bit will be set to ‘1’ in either one of
these two conditions:
1. If the receive slip buffer is emptied and a READ operation occurs,
then a full frame of data will be repeated, and this interrupt bit will be
set to ‘1’.
2. If the receive slip buffer is full and a WRITE operation occurs, then a
full frame of data will be deleted, and this interrupt bit will be set to
‘1’.
0 = Indicates that the Receive Slip Buffer Slips interrupt has not occurred
since the last read of this register.
1 = Indicates that the Receive Slip Buffer Slips interrupt has occurred
since the last read of this register.
NOTE: Users still need to read the Receive Slip Buffer Empty Interrupt (bit
1 of this register) or the Receive Slip Buffer Full Interrupts (bit 2 of
this register) to determine whether transmit slip buffer empties or
fills.
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