XRT75R12_07 Datasheet, PDF (83/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

REV. 1.0.3
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 41: XRT75R12 REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_n)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
JA RESET
Ch_n
JA1 Ch_n JA in Tx Path JA0 Ch_n
Ch_n
R/W
R/W
R/W
R/W
TABLE 42: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL n ADDRESS LOCATION = 0XM7
(n = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-4
Reserved
3
JA RESET Ch_n R/W Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure the Jitter
Attenuator (within Channel_n) to execute a RESET operation.
Whenever the user executes a RESET operation, then following will
occur.
• The READ and WRITE pointers (within the Jitter Attenuator FIFO) will
be reset to their default values.
• The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0 to 1" transition with the
appropriate write operate to set this bit-field back to "0", in order
to resume normal operation with the Jitter Attenuator.
2
JA1 Ch_n
R/W Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do
any of the following.
• To enable or disable the Jitter Attenuator corresponding to
Channel_n.
• To select the FIFO Depth for the Jitter Attenuator within Channel_n.
The relationship between the settings of these two bit-fields and the
Enable/Disable States, and FIFO Depths is presented below.
JA0 JA1
00
01
10
11
Jitter Attenuator Mode
FIFO Depth = 16 bits
FIFO Depth = 32 bits
Disabled
Disabled
80