XRT75R12_07 Datasheet, PDF (49/90 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER

REV. 1.0.3
PIN NAME
CS
RD
WR
RDY
INT
RESET
XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 14: XRT75R12 MICROPROCESSOR INTERFACE SIGNALS
TYPE
DESCRIPTION
I Chip Select Input
This active low signal selects the microprocessor interface of the XRT75R12 LIU and enables
Read/Write operations with the on-chip register locations.
I Read Signal This active low input functions as the read signal from the local µP. When this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a read operation has been
requested and begins the process of the read cycle.
I Write Signal This active low input functions as the write signal from the local µP. When this
pin is pulled “Low” (if CS is “Low”) the LIU is informed that a write operation has been
requested and begins the process of the write cycle.
O Ready Output This active low signal is provided by the LIU device. It indicates that the cur-
rent read or write cycle is complete, and the LIU is waiting for the next command.
O Interrupt Output This active low signal is provided by the LIU to alert the local mP that a
change in alarm status has occured. This pin is Reset Upon Read (RUR) once the alarm sta-
tus registers have been cleared.
I Reset Input This active low input pin is used to Reset the LIU.
7.2 Asynchronous and Synchronous Description
Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The
synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the µP that the data is available to be read by the µP, and that it is ready for the next command.
5. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6. The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local µP wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. The µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus D[7:0].
4. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
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