XRP7724 Datasheet, PDF (8/29 Pages) Exar Corporation – Quad Channel Digital PWM/PFM Programmable Power Management System

PIN ASSIGNMENT
XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
LDO3_3 1
AGND 2
CPLL 3
AVDD 4
VOUT1 5
VOUT2 6
VOUT3 7
VOUT4 8
GPIO0 9
GPIO1 10
SDA 11
XRP7724
TQFN
7mm X 7mm
Exposed Pad: AGND
33 GL_RTN2
32 GL2
31 LX2
30 GH2
29 BST2
28 GL_RTN3
27 GL3
26 LX3
25 GH3
24 BST3
23 VCCD3-4
Fig. 4: XRP7724 Pin Assignment
PIN DESCRIPTION
Name
VCC
DVDD
VCCD1-2
VCCD3-4
AGND
GL_RTN1-4
GL1-GL4
GH1-GH4
Pin Number
41
16
23,34
2
39,33, 28,22
38,32, 27,21
36,30, 25,19
Description
Input voltage. Place a decoupling capacitor close to the controller IC. This input is used
in UVLO fault generation.
1.8V supply input for digital circuitry. Connect pin to AVDD. Place a decoupling
capacitor close to the controller IC.
Gate Drive supply. Two independent gate drive supply pins where pin 34 supplies
drivers 1 and 2 and pin 23 supplies drivers 3 & 5. One of the two pins must be
connected to the LDO5 pin to enable two power rails initially. It is recommended that
the other VCCD pin be connected to the output of a 5V switching rail(for improved
efficiency or for driving larger external FETs), if available, otherwise this pin may also
be connected to the LDO5 pin. A bypass capacitor (>1uF) to PAD is recommended for
each VCCD pin with the pin(s) connected to LDO5 with shortest possible length of etch.
Analog ground pin. This is the small signal ground connection.
Ground connection for the low side gate driver. This should be routed as a signal trace
with GL. Connect to the source of the low side MOSFET.
Output pin of the low side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
Output pin of the high side gate driver. Connect directly to the gate of an external N-
channel MOSFET.
© 2012 Exar Corporation
8/29
Rev. 1.0.1