XRP7724 Datasheet, PDF (17/29 Pages) Exar Corporation – Quad Channel Digital PWM/PFM Programmable Power Management System

XRP7724
Quad Channel Digital PWM/PFM
Programmable Power Management System
an RC filter to avoid conducted noise back into
the analog circuitry.
To minimize power dissipation in the 5V LDO it
is recommended to power the drivers from an
external 5V power source either directly or by
using the V5EXT input. Good quality 1uF to
4.7uF capacitors should be connected directly
between the power pins to ground to optimize
driver performance and minimize noise
coupling to the 5V LDO supply.
The driver outputs should be connected
directly to their corresponding output
switching FETs, with the Lx output connected
to the drain of the lower FET for the best
current monitoring accuracy.
See ANP-32 “Practical Layout Guidelines for
Power^XR Designs”
LDOS
The XRP7724 has two internal Low Drop Out
(LDO) linear regulators that generate 5.0V
(LDO5) and 3.3V (LDO3_3) for both internal
and external use. Additionally it also has a
1.8V regulator that supplies power for the
XRP7724 internal circuits. Figure 3 shows a
block diagram of the linear power supplies.
LDO5 is the main power input to the device
and is supplied by an external 5.5V to 25V
(VCC) supply. The output of LDO5 should be
bypassed by a good quality capacitor
connected between the pin and ground close
to the device. The 5V output is used by the
XRP7724 as a standby power supply and is
also used to power the 3.3V and 1.8V linear
regulators inside the chip and can also supply
power to the 5V gate drivers. The total output
current that the 5V LDO can provide is 130mA.
The XRP7724 consumes approximately 20mA
and the rest is shared between LDO3_3 and
the gate drive currents. During initial power
up, the maximum external load should be
limited to 30mA.
The 3.3V LDO output available on the LDO3_3
pin is solely for customer use and is not used
internally. This supply may be turned on or off
by the configuration registers. Again a good
bypass capacitor should be used.
The AVVD pin is the 1.8V regulator output and
needs to be connected externally to the DVVD
pin on the device. A good quality capacitor
should be connected between this pin and
ground close to the package.
For operation with a VCC of 4.75V to 5.5V, the
LDO5 output needs to be connected directly to
VCC on the board.
CLOCKS AND TIMING
¸4/¸8
Reg
Clock
Divider
Ext Clock Output
GPIO1
Ext Clock Input
GPIO0
PLL
x4/x8
Reg
System Clock
Frequency
Set Reg
DPWM
Base Frequency
2x
4x
Sequencer
Freg Mult Reg
SEL
CH1 Timing
© 2012 Exar Corporation
To Channels 2®4
Fig 18 XRP7724 Timing Block Diagram
17/29
Rev. 1.0.1