XRD87L99 Datasheet, PDF (7/23 Pages) Exar Corporation – LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
xr
ELECTRICAL CHARACTERISTICS AV_DD = DV_DD = 3 V, F_S = 2 MHZ (50% DUTY CYCLE), V_REF(+) = 2.6, V_REF(-) = AGND,
T_A = 25°C, UNLESS OTHERWISE SPECIFIED
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS TEST CONDITIONS/COMMENTS
Clock to WR Hold Time
t_CLKH2
0
ns
Power Down Time¹
t_PD
300
ns
Power Up Time¹
t_PU
200
ns
Data Enable Delay
t_DEN
14
16
ns
Data High Z Delay
t_DHZ
4
6
ns
Pipeline Delay (Latency)
1.5
cycles
POWER SUPPLIES ⁸
Power Down (I_DD)
I_PD-DD
0.01
0.10
mA PD=High, CLK High or Low
Operating Voltage (AV_DD, DV_DD) V_DD
2.7
3.0
3.6
V
Current (AV_DD + DV_DD)
I_DD
7
10
mA PD=Low (Normal Mode)
V_DD =3 V
NOTES:
1 Guaranteed. Not tested.
2 Tester measures code transition voltages by dithering the voltage of the analog input (V_IN). The difference between
the measured code width and the ideal value (V_REF/1024) is the DNL error. The INL error is the maximum distance
(in LSBs) from the best fit line to any transition voltage.
3 See V_IN input equivalent circuit.
4 Clock specification to meet aperture specification (t_AP). Actual rise/fall time can be less stringent with no loss of
accuracy.
5 Specified values guarantee functional device. Refer to other parameters for accuracy.
6 System can clock the XRD87L99 with any duty cycle as long as all timing conditions are met.
7 Input range where input is converted correctly into binary code. Input voltage outside specified range converts to
zero or full scale output.
8 DV_DD and AV_DD are connected through the silicon substrate. Connect together at the package.
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
7