XRD87L99 Datasheet, PDF (12/23 Pages) Exar Corporation – LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

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XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
FIGURE 10. RELATIONSHIP OF DATA TO CLOCK
CLOCK N
N+1
DATA
N
N+1
a. Continuous sampling
CLOCK
DATA
N
b. Single sampling
BALANCE
N
1.3 ANALOG INPUT
The XRD87L99 has very flexible input range charac-
teristics. The user may set V_REF(+) and V_REF(-) to two
fixed voltages and then vary the input DC and AC lev-
els to match the VREF range. Another method is to
first design the analog input circuitry and then adjust
the reference voltages for the analog input range.
One advantage is that this approach may eliminate
the need for external gain and offset adjust circuitry
which may be required by fixed input range A/Ds.
The XRD87L99's performance is optimized by using
analog input circuitry that is capable of driving the A_IN
input. Figure 11 shows the equivalent circuit for A_IN.
FIGURE 11. ANALOG INPUT EQUIVALENT CIRCUIT
AV_DD
A_IN
R Series
200 Ω
4
R MUX
200 Ω
10 pF
1 pF
8
10 pF
Control
Channel
Selection
80 Ω
50 Ω
φS
φS
10 pF
φB
1 pF
160 Ω
+
1/2 [ V_{REF(+) +} V_REF(-) ]
1.4 ANALOG INPUT MULTIPLEXER
The XRD87L99 includes a 8-Channel analog input
multiplexer. The relationship between the clock, the
multiplexer address, the WR and the output data is
shown in Figure 12.
FIGURE 12. MUX ADDRESS TIMING
Clock
Sample N
Old Address
t_CLKS2
WR
t_AS
Sample M
New Address
t_WR
t_CLKH2
t_AH
Sample
M+1
Address
DB0-DB9 N-2 Valid
N-1 Valid
Old Address
Note: t_CLKS2 = t_CLKH2 = 0
N Valid
Old Address
M Valid
New Address
FIGURE 13. ANALOG MUX TIMING
A2, A1, A0
WR
MUXEN
(Internal Signal)
t_AS
t_AH
t_WR
t_MUXEN1
1.5 REFERENCE VOLTAGES
The input/output relationship is a function of V_REF:
A_IN = V_IN - V_REF(-)
V_REF = V_REF(+) - V_REF(-)
DATA = 1024 * (A_IN/V_REF)
A system can increase total gain by reducing V_REF.
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