XRD87L99 Datasheet, PDF (14/23 Pages) Exar Corporation – LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

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XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
2.0 APPLICATION NOTES
FIGURE 16. TYPICAL CIRCUIT CONNECTIONS
C1 = 4.7 or 10µF Tantalum
C2 = 0.1µF Chip Cap or low inductance cap
R_T = Clock Transmission Line Termination
+5 V
+
Reference
Voltage
Source
-
1 of 8
Z < 100Ω
C1A, C2A
AV_DD
AIN1 ^(Substrate)
C1D, C2D
DV_DD
OFW
Buffer
A_IN
Resistive
Isolation of
50 to 100 Ω
C1 C2
C1 C2
C1
C2
AIN8
DB9 - DB0
XRD87L99
OE
V_REF(+)
3/4 R
1/4 R
WR
CLK
CLK
R_T
V_REF(-)
A2
V_REF1(-)
A1
AGND DGND
A0
The following information will be useful in maximizing
the performance of the XRD87L99.
1. All signals should not exceed AV_DD +0.5 V or
AGND -0.5 V or DV_DD +0.5 V or DGND -0.5 V.
2. Any input pin which can see a value outside the
absolute maximum ratings (AV_DD or DV_DD+0.5 V
or AGND -0.5 V) should be protected by diode
clamps (HP5082-2835) from input pin to the sup-
plies. All XRD87L99 inputs have input protection
diodes which will protect the device from short
transients outside the supply ranges.
3. The design of a PC board will affect the accuracy
of XRD87L99. Use of wire wrap is not recom-
mended.
4. The analog input signal (V_IN) is quite sensitive
and should be properly routed and terminated. It
should be shielded from the clock and digital out-
puts so as to minimize cross coupling and noise
pickup.
5. The analog input should be driven by a low
impedance (less than 50Ω).
6. Analog and digital ground planes should be sub-
stantial and common at one point only. The
ground plane should act as a shield for parasitics
and not a return path for signals. To reduce noise
levels, use separate low impedance ground
paths. DGND should not be shared with other
digital circuitry. If separate low impedance paths
cannot be provided, DGND should be connected
to AGND next to the XRD87L99.
7. DV_DD should not be shared with other digital cir-
cuitry to avoid conversion errors caused by digital
supply transients. DV_DD for the XRD87L99 should
be connected to AV_DD next to the XRD87L99.
8. DV_DD and AV_DD are connected inside the
XRD87L99. DGND and AGND are connected
internally.
9. Each power supply and reference voltage pin
should be decoupled with a ceramic (0.1µF) and
a tantalum (10µF) capacitor as close to the
device as possible.
10. The digital output should not drive long wires.
The capacitive coupling and reflection will con-
tribute noise to the conversion. When driving dis-
tant loads, buffers should be used. 100Ω resis-
tors in series with the digital outputs in some
applications reduces the digital output disruption
of A_IN.
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