XRD87L99 Datasheet, PDF (13/23 Pages) Exar Corporation – LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX

XRD87L99
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.0.0
xr
1.6 DIGITAL INTERFACES
The logic encodes the outputs of the comparators in-
to a binary code and latches the data in a D-type flip-
flop for output.
The functional equivalent of the XRD87L99 (Figure
14) is composed of:
1. Delay stage (t_AP) from the clock to the sampling
phase (f_S).
2. An ideal analog switch which samples V_IN.
3. An ideal A/D which tracks and converts V_IN with
no delay.
4. A series of two DFF's with specified hold (t_HLD)
and delay (t_DL) times.
t_AP, t_HLD and t_DL are specified in the Electrical Charac-
teristics table.
1.7 POWER DOWN
Figure 15 shows the relationship between the clock,
sampled V_IN to output data relationship and the effect
of power down.
FIGURE 14. XRD87L99 FUNCTIONAL EQUIVALENT
CIRCUIT AND INTERFACE TIMING
φ_S
VIN
A/D
DQ
DQ
DB9-DB0
t_AP
XRD8799
CLK
VIN
DB9-DB0
N
t_DL
N+1
t_HLD
N-1
CLK
N
FIGURE 15. POWER DOWN TIMING DIAGRAM
CLK
SAMPLE
N
VIN
DB0-DB9 N-2 Valid
PD
IDD, IVREF(+)
N-1 Valid
t_CLKS1
SAMPLE
M
N Valid
t_CLKH1
t_PD
t_PU
SAMPLE
M+1
M Valid
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