XRP7708_12 Datasheet, PDF (6/28 Pages) Exar Corporation – Quad Channel Digital PWM Step Down Controllers

PIN ASSIGNMENT
XRP7708 and XRP7740
Quad Channel Digital PWM Step Down Controllers
AVDD 1
DVDD 2
GPIO0 3
GPIO1 4
GPIO2 5
GPIO3 6
GPIO4_SDA 7
GPIO5_SCL 8
ENABLE 9
DGND 10
XRP7708
XRP7740
TQFN
6mm X 6mm
Exposed Pad: AGND
30 GL2
29 LX2
28 GH2
27 BST2
26 VCCD
25 BST4
24 GH4
23 LX4
22 GL4
21 PGND4
Fig. 3: XRP7708/40 Pin Assignment
PIN DESCRIPTION
Name
VIN1
VIN2
VCCA
VCCD
PGND1- PGND4
AVDD
DVDD
Pin Number
Description
39
38
37
26
36,31,16,21
1
2
Power source for the internal linear regulators to generate VCCA, VDD and the Standby
LDO (LDOOUT). Place a decoupling capacitor close to the controller IC. Also used in
UVLO1 fault generation – if VIN1 falls below the user programmed limit, all channels are
shut down. The VIN1 pin needs to be tied to VIN2 on the board with a short trace.
If the Vin2 pin voltage falls below the user programmed UVLO VIN2 level all channels are
shut down. The VIN2 pin needs to be tied to VIN1 on the board with a short trace.
Output of the internal 5V LDO. This voltage is internally used to power analog blocks. This
pin should be bypassed with a minimum of 4.7uF to AGND
Gate Drive input voltage. This is not an output voltage. This pin can be connected to
VCCA to provide power for the Gate Drive. VCCD should be connected to VCCA with the
shortest possible trace and decouple with a minimum 1µF capacitor. Alternatively, VCCD
could be connected to an external supply (not greater than 5V).
GL return connection. Ground connection for the low side gate driver. Connect at low side
FET source. Connecting to the ground plane at the chip will inject noise into the local
ground resulting in potential I²C communications problems and PWM jitter.
Output of the internal 1.8V LDO. A decoupling capacitor should be placed between AVDD
and AGND close to the chip (with short traces).
Input for powering the internal digital logic. This pin should be connected to AVDD.
© 2012 Exar Corporation
6/28
Rev. 1.2.2