XRP7708_12 Datasheet, PDF (18/28 Pages) Exar Corporation – Quad Channel Digital PWM Step Down Controllers

XRP7708 and XRP7740
Quad Channel Digital PWM Step Down Controllers
CHIP OPERATION AND CONFIGURATION
SOFT-START
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the
ramp characteristics for a specific channel. This register allows the customer to program the
channel with a 250us step resolution and up to a maximum 16ms delay.
Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit
represents 250us steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the
number of microseconds for each 50mV increment to reach the target voltage. The status of the
soft-start operation is indicated in the POWER_GOOD_SOFT_START_FLAG register by bits [3:0]
which correspond to channels 4 though 1 respectively. A value of 1 signifies that a soft start is in
operation on a given channel.
Enable
Signal
Vout
DELAY
Bit [10:15]
RISE TIME
Bit [0:9]
SS_RISE_CHx
REGISTER
Fig. 20: Channel Power Up Sequence
SOFT-STOP
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250us steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
Enable
Signal
Vout
© 2012 Exar Corporation
DELAY
Fall Time
Bit [10:15]
PD_DELAY_CHx
REGISTER
Bit [0:9]
Fig. 23: Channel Soft-Stop Sequence
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Rev. 1.2.2