XRP7708_12 Datasheet, PDF (25/28 Pages) Exar Corporation – Quad Channel Digital PWM Step Down Controllers

XRP7708 and XRP7740
Quad Channel Digital PWM Step Down Controllers
I1 is the step load low current
Vos is output voltage including the overshoot
Vout is the steady state output voltage
Or it can be expressed approximately by
𝐶
=
𝐿
×
2
(𝐼₂ − 𝐼₁)²
× 𝑉𝑜𝑢𝑡 − ∆𝑉
Here, ∆V = V_os − V_out is the overshoot voltage deviation.
Select ESR such that output voltage ripple (Vrip) specification is met. There are two components in
Vrip. First component arises from the charge transferred to and from Cout during each cycle. The
second component of Vrip is due to the inductor ripple current flowing through the output
capacitor’s ESR. It can be calculated for Vrip:
1
𝑉𝑟𝑖𝑝 = 𝐼𝑟𝑖𝑝 × �𝐸𝑆𝑅² + �_{8 × 𝐶𝑜𝑢𝑡 × 𝑓𝑠�}
Where:
Irip is the inductor ripple current
fs is the switching frequency
Cout is the output capacitance
Note that a smaller inductor results in a higher Irip, therefore requiring a larger Cout and/or lower
ESR in order to meet Vrip.
• Input Capacitor Selection
Select the input capacitor for Voltage, Capacitance, ripple current, ESR and ESL. Voltage rating is
nominally selected to be at least twice the input voltage. The RMS value of input capacitor current,
assuming a low inductor ripple current, can be approximated as:
𝐼𝑖𝑛 = 𝐼𝑜𝑢𝑡 × �𝐷 × (1 − 𝐷)
Where:
Iin is the RMS input current
Iout is the DC output current
D is the duty cycle
In general, the total input voltage ripple should be kept below 1.5% of VIN. The input voltage
ripple also has two major components: the voltage drop on the main capacitor ∆V_Cin and the
voltage drop due to ESR - ∆V_ESR . The contribution to Input voltage ripple by each term can be
calculated from:
∆V_Cin
=
I V _{out out} (V_in − V_out )
f _sC_inV_in²
∆V_ESR = ESR ⋅ (I_out + 0.5I_rip )
© 2012 Exar Corporation
25/28
Rev. 1.2.2