SP6132H Datasheet, PDF (6/14 Pages) Sipex Corporation – High Voltage, 300KHz Synchronous PWM Controller

THEORY OF OPERATION: Continued
Error Amplifier and Voltage Loop
As stated before, the heart of the SP6132H
voltage error loop is a high performance, wide
bandwidth transconductance amplifier. Be-
cause of the amplifier’s current limited (+150µA)
transconductance, there are many ways to com-
pensate the voltage loop or to control the COMP
pin externally. If a simple, single pole, single
zero response is required, then compensation
can be as simple as an RC circuit to ground. If a
more complex compensation is required, then
the amplifier has enough bandwidth (45° at 4
MHz) and enough gain (60dB) to run Type III
compensation schemes with adequate gain and
phase margins at cross over frequencies greater
than 50kHz.
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is an asynchronous start
up mode. Basically, the GL driver cannot turn
on unless the GH driver has attempted to turn on
or the SS pin has exceeded 1.7V. This feature
prevents the controller from “dragging down”
the output voltage during startup or in fault
modes. The second feature is a 100% duty cycle
timeout that ensures synchronized refreshing of
the BST capacitor at very high duty ratios. In the
event that the GH driver is on for 20 continuous
clock cycles, a reset is given to the PWM flip
flop half way through the 21st cycle. This forces
GL to rise for the remainder of the cycle, in turn
refreshing the BST capacitor.
Gate Drivers
The SP6132H contains a pair of powerful 2Ω
SOURCE and 1.5Ω SINK drivers. These state-
of-the-art drivers are designed to drive external
NFETs capable of handling up to 30A. Rise,
fall, and non-overlap times have all been minized
to achieve maximum efficiency. All drive pins
GH, GL & SWN are monitored continuously to
ensure that only one external NFET is ever on at
any given time.
GATE DRIVER TEST CONDITIONS
90%
GH(GL) _2V
10%
FALL TIME
GL(GH)
90%
2V
RISE TIME
10%
V(BST)
GH
Voltage
V(SWN)
V(VCC)
GL
Voltage
0V
V(VIN)
SWN
Voltage
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
NON-OVERLAP
TIME
Date:2/14/06
SP6132H High Voltage, Synchronous PWM Controller
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© Copyright 2006 Sipex Corporation