SP6132H Datasheet, PDF (4/14 Pages) Sipex Corporation – High Voltage, 300KHz Synchronous PWM Controller

FUNCTIONAL DIAGRAM
5 COMP
100% Protection Logic
VCC
PWM LOOP
PULSES ^CLR
COUNT 20
CLOCK
CLK
FAULT
VFB
VCC
Gm ERROR AMPLIFIER
VFBINT
VCC
VPOS ^Gm
FAULT
10 µA
SS 7
SOFTSTART INPUT
POS REF
FAULT
FAULT
RESET
DOMINANT
R
Q
S
QPWM
RAMP = 1.1V
0.4 V
300 kHZ
CLK
CLOCK PULSE GENERATOR
V_CC 1
REFERENCE
CORE
0.8V
REF OK
1.7 V
SS
1.7 V
ASYNC. STARTUP
COMPARATOR
SYNCHRONOUS
DRIVER
GL HOLD OFF
10 BST
9 GH
8 SWN
2 GL
3 GND
145 ˚C ON
135 ˚C OFF
THERMAL
SHUTDOWN
VPOS
VFBINT
0.25 V
+-
SHORT CIRCUIT
DETECTION
+
-
SET
DOMINANT
S
Q
R
HICCUP FAULT
REF OK
VCC
+
4.25 V ON
4.05 V OFF -
VCC UVLO
POWER FAULT
FAULT
+
2.50 VON
2.20 V OFF
-
VIN UVLO
CLK
COUNTER _{200ms Delay}
6
UVIN
CLR
REF OK
THERMAL AND SHORT CIRCUIT PROTECTION
UVLO COMPARATORS
THEORY OF OPERATION
General Overview
The SP6132H is a fixed frequency, voltage
mode, synchronous PWM controller optimized
for high efficiency. The part has been designed
to be especially attractive for split plane applica-
tions which utilize 5V to power the controller
and 3V to 12V for step down conversion.
The heart of the SP6132H is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. A precision 0.8V reference present on
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the V_FB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp and PWM
control logic are governed by the internal oscil-
lator that accurately sets the PWM frequency to
300kHz.
The SP6132H contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The SP6132H also contains a number of valu-
able protection features. A programmable input
(V_IN) UVLO allows a user to set the exact value
at which the conversion voltage is at a safe point
to begin down conversion, and an internal V_CC
UVLO ensures that the controller itself has
enough voltage to properly operate. Other pro-
Date:2/14/06
SP6132H High Voltage, Synchronous PWM Controller
4
© Copyright 2006 Sipex Corporation