SP6132H Datasheet, PDF (10/14 Pages) Sipex Corporation – High Voltage, 300KHz Synchronous PWM Controller

APPLICATIONS INFORMATION: Continued
thermal improvement can be achieved in the maxi-
mum power dissipation through the proper design
of copper mounting pads on the circuit board. For
example, in an SO-8 package, placing two 0.04
square inches of copper pad directly under the
package, without occupying additional board space,
can increase the maximum power from approxi-
mately 1 to 1.2W. For DPAK package, enlarging
the tap mounting pad to 1 square inch reduces the
R_ΘJA from 96°C/W to 40°C/W.
Schottky Diode Selection
When paralleled with the bottom MOSFET, an
optional Schottky diode can improve efficiency
and reduce noise. Without this Schottky diode,
the body diode of the bottom MOSFET con-
ducts the current during the non-overlap time
when both MOSFETs are turned off. Unfortu-
nately, the body diode has high forward voltage
and reverse recovery problems. The reverse
recovery of the body diode causes additional
switching noises when the diode turns off. The
Schottky diode alleviates these noise sources
and additionally improves efficiency thanks to
its low forward voltage. The reverse voltage
across the diode is equal to input voltage, and the
diode must be able to handle the peak current
equal to the maximum load current.
The power dissipation of the Schottky diode is
determined by:
P_DIODE = 2V_FI_OUTT_NOLF_S
where
T_NOL = non-overlap time between GH and GL.
V_F = forward voltage of the Schottky diode.
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the selected frequency FCO, the gain of
the error amplifier must compensate for the
attenuation caused by the rest of the loop at this
frequency.
+ V_REF
(Volts) _
Type III Voltage Loop
Compensation
G_AMP (s) Gain Block
(SRz2Cz2+1)(SR1Cz3+1)
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
PWM Stage
G_PWM Gain
Block
V_IN
V_{RAMP_PP}
Notes: R_ESR = Output Capacitor Equivalent Series Resistance.
R_DC = Output Inductor DC Resistance.
V_{RAMP_PP} = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> R_ESR & R_DC
Voltage Feedback
G_FBK Gain Block
V_FBK
(Volts)
R_{2 or}
(R_{1 +} R₂)
V_REF
V_OUT
SP6132H Voltage Mode Control Loop with Loop Dynamic
Output Stage
G_OUT (s) Gain
Block
(SR_ESRC_OUT+ 1)
[S^2LC_OUT+S(R_ESR+R_DC) C_OUT+1]
V_OUT
(Volts)
Date:2/14/06
SP6132H High Voltage, Synchronous PWM Controller
10
© Copyright 2006 Sipex Corporation