DAN-170 Datasheet, PDF (6/7 Pages) Exar Corporation – MIGRATING TO EXAR’S FIFTH GENERATION UARTS

DATA COMMUNICATIONS APPLICATION NOTE
DAN170
As is clearly seen above, the interrupt routine is inefficient since it has to loop through all channels to determine
the cause of the interrupt. Also, only one interrupt for the entire device can be serviced at once. If two of these
devices are used, the scheme becomes even more inefficient. This inherent latency is not seen in the interrupt
service routine for the XR16L784/788 because of the availability of global interrupt registers paving the way for
servicing multiple interrupting conditions per interrupt.
4.2 INTERRUPT SERVICE ROUTINE FOR XR16L784/788
Interrupt_Routine_788 () {
Disable_Interrupts();
source_channel = read (INT0); // bit-0 = 1 indicates an interrupt pending for channel 0, etc
/* 3-bit encoding per channel making it 12-bits for the XR16L784 and 24-bits for XR16L788 */
/* In this encoding, bits 2:0 are for channel 0, bits 5:3 are for channel 1 etc. */
/* or you can read the same info from ISR register of the channel - but the encoding IS NOT THE SAME.
Please read the datasheet of the XR16L784 or XR16L788 for more information */
long interrupt_info = ( ( (read (INT3) << 8) | read (INT2)) << 8) | read (INT1); // 24 bits for the XR16L788
if (source_channel & 0x01) {
// bit-0 is channel 0, bit-7 is channel 7 etc.
switch (interrupt_info & 0x7)
{
case RXRDY :
Read bytes out of RHR;
break;
case TXRDY :
Load bytes into THR;
break;
Other cases :
......
case No_Interrupt :
break;
// go to next channel
}
// end switch statement for channel 0
}
// end if (source_channel & 0x01)
if (source_channel & 0x02)
{
switch (interrupt_info & 0x38) {
......
.....
}
// bits 5:3 of the 12 or 24-bit value for channel 1
......
// service all channel interrupts similarly
Enable_Interrupts();
}
// End of Interrupt_Routine()
The above scheme provides the following advantages:
q Global interrupt registers support quicker interrupt source identification.
q Interrupts from multiple channels can be serviced per interrupt, according to the priority assigned to each
channel.
q Shorter and deterministic time inside the interrupt service routine due to fewer reads of status registers (a
maximum of 4 registers, INT0-INT3 as against a maximum of 8 ISR registers of individual channels).
6