DAN-170 Datasheet, PDF (4/7 Pages) Exar Corporation – MIGRATING TO EXAR’S FIFTH GENERATION UARTS

DATA COMMUNICATIONS APPLICATION NOTE
DAN170
FIGURE 2. CPU-UART INTERFACE WHEN USING TWO ST16C454/554/654/854/864’S VS. ONE XR16L788
Data Bus D7:D0
5 or 3.3V
VCC
Address Bus
CPU
IRQ
A10:A0
Interrupt
Controller
Logic*
Programmable
Logic Device*
A2:A0
CSA#
CSB#
CSC#
CSD#
ST16C454
ST16C554
ST16C654
XR16C854
XR16C864
INTA
INTB
INTC
INTD
GND
5 or 3.3V
VCC
Data Bus D7:D0
A2:A0
CSA#
CSB#
CSC#
CSD#
ST16C454
ST16C554
ST16C654
XR16C854
XR16C864
INTA
INTB
INTC
INTD
GND
2A) Typical Connections between the CPU and Two ST16C454/554/654/854/864’s
5V Tolerant Inputs
5 or 3.3V
VCC
Data Bus D7:D0
Address Bus A7:A0
CPU
ChipSelect^†
IRQ
VCC
47 - 100kΩ
XR16L788
CS#
INT#
GND
2B) Typical Connections between the CPU and One XR16L788
* Since there are eight chipselects and eight interrupts, external glue logic is essential.
†_{One of the chipselect outputs from the CPU can usually be used to drive the CS# pin of the XR16L788.}
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