DAN-170 Datasheet, PDF (1/7 Pages) Exar Corporation – MIGRATING TO EXAR’S FIFTH GENERATION UARTS

DATA COMMUNICATIONS APPLICATION NOTE
DAN170
AUGUST 2004
MIGRATING TO EXAR’S FIFTH GENERATION UARTS: XR16L784/788
Author: BL
1.0 INTRODUCTION
This application note provides sytem design engineers with the information necessary to migrate to Exar’s
newer and more powerful Fifth Generation UARTs. It describes the hardware and software differences be-
tween the classic four channel UARTs (ST16C454, ST16C554, ST16C654, XR16C854 and XR16C864) and
the newer fifth generation UARTs (XR16L784 Quad UART and XR16L788 Octal UART) which provide:
q easier hardware interface
q easier software programming
q higher perfomance in interrupt service routine
q register compatibility to the industry standard 16550
2.0 ADVANTAGES OF THE FIFTH GENERATION XR16L784 AND XR16L788
The upgrade path from one or two ST16C454/554/654/854/864 to an XR16L784 or XR16L788 offers the fol-
lowing benefits:
q Simpler hardware interface with Intel/Motorola CPU
q Reduction in board space (when moving from two ST16C454/554/654/854/864’s to one XR16L788)
q Ability to interface with both 3.3V and 5V devices (5V Tolerant inputs)
q Higher baud rate via 8X sampling
q Fifth generation Flat Register Set, No shadow/mirror registers
q Global Interrupt Source Registers for easier/faster interrupt handling
It is to be noted that the fifth generation devices continue to offer the same advantages as the classic devices
in the following aspects:
q Each channel is independent and has its own TX and RX FIFOs
q Each channel has a 16550-compatible register set
q Each channel has its own baud rate selection
q All channels use XTAL1 clock as the input clock for baud rate generation
3.0 HARDWARE DIFFERENCES
The newer XR16L78x UARTs enable simpler interfacing with a CPU and/or a programmable logic device. Let
us consider two common cases:
q migrating from one ST16C454/554/654/854/864 to one XR16L784
q migrating from two ST16C454/554/654/854/864’s to one XR16L788
Tables 1 and 2 describe the footprint and hardware differences for both the cases. Figures 1 and 2 show the
connections required for a CPU-UART interface for both the cases.
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