XR16V798_08 Datasheet, PDF (56/56 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL

XR16V798
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
3.1.2.2 TIMER [7:0] RESERVED....................................................................................................................................... 24
3.1.2.3 TIMERCNTL [7:0] REGISTER .............................................................................................................................. 24
TABLE 10: TIMER CONTROL COMMANDS ....................................................................................................................................... 24
TIMER OPERATION ................................................................................................................................................ 25
FIGURE 14. TIMER/COUNTER CIRCUIT............................................................................................................................................. 25
FIGURE 15. INTERRUPT OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES................................................................................. 25
3.1.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 26
3.1.4 REGA [7:0](DEFAULT 0X00) ....................................................................................................................................... 26
3.1.5 RESET [7:0] (DEFAULT 0X00) ..................................................................................................................................... 26
3.1.6 SLEEP [7:0] (DEFAULT 0X00) ..................................................................................................................................... 26
3.1.7 DEVICE IDENTIFICATION AND REVISION ................................................................................................................. 26
3.1.7.1 DVID [7:0] (DEFAULT 0X48) ................................................................................................................................. 27
3.1.7.2 DREV [7:0] (DEFAULT (0X01) .............................................................................................................................. 27
3.1.8 REGB [7:0] (DEFAULT 0X00) ...................................................................................................................................... 27
3.2 UART CHANNEL CONFIGURATION REGISTERS .......................................................................................... 28
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 28
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 29
4.0 INTERNAL REGISTER DESCRIPTIONS............................................................................................... 30
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 30
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY................................................................................ 30
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 30
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 30
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 30
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY................................................................................... 32
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 32
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 32
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 32
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 33
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 34
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 34
TABLE 15: PARITY PROGRAMMING .................................................................................................................................................. 35
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 36
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 37
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 38
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY .................................................................................... 39
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 39
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 40
4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE............................................................................ 40
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 41
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 41
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 43
4.14 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 43
4.15 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 43
4.16 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 43
4.17 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY................................................................... 43
4.18 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 43
4.19 XCHAR REGISTER, READ ONLY .................................................................................................................. 44
TABLE 19: UART RESET CONDITIONS ...................................................................................................................................... 45
ABSOLUTE MAXIMUM RATINGS.................................................................................. 46
ELECTRICAL CHARACTERISTICS ............................................................................... 46
DC ELECTRICAL CHARACTERISTICS ............................................................................................................. 46
AC ELECTRICAL CHARACTERISTICS ............................................................................................................. 47
FIGURE 16. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING ................................................................................................. 49
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING ........................................................................................ 50
FIGURE 18. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 51
FIGURE 19. RECEIVE INTERRUPT TIMING [NON-FIFO MODE]........................................................................................................... 51
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]......................................................................................................... 52
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]................................................................................................................... 52
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]................................................................................................................. 52
PACKAGE DIMENSIONS................................................................................................ 53
REVISION HISTORY...................................................................................................................................... 54
TABLE OF CONTENTS...................................................................................................... I
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