XR16V798_08 Datasheet, PDF (32/56 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL

XR16V798
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
4.4 Interrupt Status Register (ISR) - Read Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table, Table 13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4. See IER bit-2 description above.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by a 4-char plus 12 bits delay timer.
• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
• MSR is by any of the MSR bits 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit-7 and selection on MCR bit-2.
• RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit-6 and selection on MCR bit-2.
4.4.2 Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out interrupt is cleared by reading RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
• Xon or Xoff interrupt is cleared by a read to ISR register.
• Special character interrupt is cleared by a read to ISR or after the next character is received.
• RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
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TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
1
0
0
0
1
1
0 LSR (Receiver Line Status Register)
2
0
0
0
1
0
0 RXRDY (Received Data Ready)
3
0
0
1
1
0
0 RXRDY (Receive Data Time-out)
4
0
0
0
0
1
0 TXRDY (Transmitter Holding Register Empty)
5
0
0
0
0
0
0 MSR (Modem Status Register)
6
0
1
0
0
0
0 RXRDY (Received Xon/Xoff or Special character)
7
1
0
0
0
0
0 CTS#/DSR#, RTS#/DTR# change of state
X
0
0
0
0
0
1 None (default) or wake-up indicator
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