XR16V798_08 Datasheet, PDF (17/56 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL

XR16V798
REV. 1.0.1
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
In the event that the receive buffer is overfilling and flow control needs to be executed, the 798 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 798 sends the Xoff-
1,2 characters two character times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the
798 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level
below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto
RTS/DTR Hysteresis value in Table 17. Table 6 below explains this when Trigger Table-B (See Table 14) is
selected.
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL INT PIN ACTIVATION
8
8
16
16
24
24
28
28
XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
8*
16*
24*
28*
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
0
8
16
24
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.12 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data. The 798 compares each incoming receive character with Xoff-2 data. If a match exists, the
received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character.
Although the Internal Register Table shows Xon, Xoff Registers with 8 bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the
number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1
also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds to the LSB bit for the receive character.
2.13 Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. It asserts RTS# or DTR# (LOW) after a specified delay indicated in MSR[7:4] following the last stop bit of
the last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. When the host is ready to transmit next polling data packet again,
it only has to load data bytes to the transmit FIFO. The transmitter automatically de-asserts RTS# or DTR#
output (HIGH) prior to sending the data. The auto RS485 half-duplex direction control also changes the
transmitter empty interrupt to TSR empty instead of THR empty.
2.14 Infrared Mode
Each UART in the 798 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to start up in the
infrared mode. Note that the ENIR pin is sampled when the RST# input is de-asserted. This global control pin
enables the MCR bit-6 function in every UART channel register. After power up or a reset, the software can
overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable the receiver while the transmitter is
sending data. This prevents echoed data from reaching the receiver. The global activation ENIR pin prevents
the infrared emitter from turning on and drawing large amount of current while the system is starting up. When
the infrared feature is enabled, the transmit data outputs, TX[7:0], would idle at logic zero level. Likewise, the
RX [7:0] inputs assume an idle level of logic zero.
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