XR16V798_08 Datasheet, PDF (16/56 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL

XR16V798
HIGH PERFORMANCE 2.25V TO 3.6V OCTAL UART WITH FRACTIONAL BAUD RATE
REV. 1.0.1
FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART
UARTA
Receiver FIFO
Trigger Reached
RXA
TXB
Remote UART
UARTB
Transmitter
Auto RTS
Trigger Level
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto CTS
Monitor
Receiver FIFO
Trigger Reached
Auto CTS
Monitor
CTSA#
RTSB#
Auto RTS
Trigger Level
RTSA#
CTSB#
TXB
Assert RTS# to Begin
Transmission
1
ON
2
7
ON
3
OFF
8 ^OFF
10 ON
11
ON
Data Starts
4
6 _Suspend ^Restart
9
RXA FIFO
Receive
INTA
(RXA FIFO
Data ^{RX FIFO}
5
Trigger Level
Interrupt)
RTS High
Threshold
RTS Low
Threshold
RX FIFO
12 _{Trigger Level}
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
2.11 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 18), the 798 compares one or two sequential receive data
characters with the programmed Xon-1,2 or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed Xoff-1,2 value(s), the 798 will halt transmission (TX) as soon as the current character has
completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the
interrupt output pin will be activated. Following a suspension due to a match of the Xoff character(s), the 798
will monitor the receive data stream for a match to the Xon-1,2 character(s). If a match is found, the 798 will
resume operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon1, Xon2, Xoff1 and Xoff2 flow control registers to ’0’. Following reset,
any desired Xon/Xoff value can be used for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 18) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the 798 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
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