XR17D152 Datasheet, PDF (55/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

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REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
AC ELECTRICAL CHARACTERISTICS FOR 3.3V PCI BUS INTERFACE (VIO = 3.0-3.6V, VCC = 3.0-5.5V)
TA=0^o to 70^oC (-40^o to +85^oC for industrial grade package).
SYMBOL
PARAMETER
MIN
MAX
UNITS
NOTES
XTAL1
XTAL2
Crystal Frequency
24
MHz
On-chip osc.
ECLK
External Clock
33
MHz
VCC = 3.3V ±10%
50
MHz
VCC = 5V ±10%
T_ECLK
External Clock Period
30
(T_ECLK = 1/ECLK)
20
ns
VCC = 3.3V ±10%
ns
VCC = 5V ±10%
T_ECH, T_ECL External Clock High/Low
13
Time
8
ns
VCC = 3.3V ±10%
ns
VCC = 5V ±10%
I_OH(AC)
Switching Current High
-12VIO
mA See PCI Specification
Rev. 2.3
I_OL(AC)
Switching Current Low
16VIO
mA See PCI Specification
Rev. 2.3
I_CH
High Clamp Current
I_CL
Low Clamp Current
25+(Vin-VIO-1)/0.015
-25+(Vin+1)/0.015
mA
VIO+4 > Vin ≥ VIO+1
mA
-3 < Vin ≤ -1
Slew_R
Slew_F
T_CYC
Output Rise Slew Rate
Output Fall Slew Rate
CLK Cycle Time
1
4
V/ns 0.2VIO - 0.6VIO load
1
4
V/ns 0.6VIO - 0.2VIO load
30
∞
ns
PCI Bus Clock, CLK
T_HI
CLK High Time
11
ns
T_LO
CLK Low Time
11
ns
CLK Slew Rate
1
4
V/ns
T_VAL
CLK to Signal Valid Delay
2
11
ns
T_ON
Float to Active Delay
2
ns
T_OFF
Active to Float Delay
28
ns
T_SETUP
Input Setup Time to CLK -
7
ns
bused signals
T_HOLD
Input Hold Time from CLK
0
ns
T_PRST
RST# Active Time After
1
ms
Power Stable
T_CRST#
RST# Active Time After CLK
100
us
Stable
RST# Slew Rate
50
mV/ns
55