XR17D152 Datasheet, PDF (27/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

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REV. 1.2.0
XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
5.2 Transmitter
The transmitter section comprises of 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-
bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte from
the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
5.2.1 Transmit Holding Register (THR) - Write-Only
The Transmit Holding Register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
5.2.2 Transmitter Operation in non-FIFO mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE
D a ta
B y te
16X or 8X
C lock
(8XM ODE
R egister)
Transm it
H olding
R egister
(T H R )
TH R Interrupt (ISR bit-1)
Enabled by IER bit-1
Transm it Shift R egister (TSR)
M
L
S
S
B
B
T X N O F IF O 1
5.2.3 Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
5.2.4 Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled during
powerup or reset by the EN485# pin or in software by FCTR bit-5. While transmitting, the RTS# or DTR# signal
is HIGH. The RTS# or DTR# signal changes from a HIGH to a LOW after a specified delay indicated in
MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around
the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last
transmission to reach the farthest station on a long cable network before switching off the line driver. This delay
prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter
empty interrupt to TSR empty instead of THR empty.
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