XR17D152 Datasheet, PDF (12/68 Pages) Exar Corporation – UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART

XR17D152
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
áç
REV. 1.2.0
TABLE 2: XR17D152 DEVICE CONFIGURATION REGISTERS
OFFSET ADDRESS
MEMORY SPACE
READ/WRITE
DATA WIDTH
COMMENT
0x000 - 0x00F
UART channel 0 Regs (Table 11 & Table 12) 8/16/24/32 First 8 regs are 16550 compatible
0x010 - 0x07F
Reserved
0x080 - 0x093
DEVICE CONFIG.
REGISTERS
(Table 3)
8/16/24/32
0x094 - 0x0FF Reserved
Read/Write
0x100 - 0x13F
UART 0 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
0x100 - 0x13F
UART 0 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
0x140 - 0x17F
Reserved
0x180 - 0x1FF
UART 0 – Read FIFO
with status
Read-Only
16/32
64 bytes of RX FIFO data + 64 bytes
of LSR status information
0x200 - 0x20F
0x210 - 0x2FF
0x300 - 0x33F
0x300 - 0x33F
0x340 - 0x37F
0x380 - 0x3FF
UART channel 1 Regs (Table 11 & Table 12) 8/16/24/32 First 8 regs are 16550 compatible
Reserved
Read/Write
UART 1 – Read FIFO
Read-Only
8/16/24/32 64 bytes of RX FIFO data
UART 1 – Write FIFO
Write-Only
8/16/24/32 64 bytes of TX FIFO data
Reserved
UART 1 – Read FIFO
with status
Read-Only
16/32
64 bytes of RX FIFO data + 64 bytes
of LSR status information
ADDRESS
[A7:A0]
Ox080
Ox081
Ox082
Ox083
TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
REGISTER
READ/WRITE COMMENT
RESET STATE
INT0 [7:0]
INT1 [15:8]
INT2 [23:16]
INT3 [31:24]
Read-only Interrupt [1:0], Reserved [7:2]
Read-only [5:0], Reserved [7:6]
Reserved
Reserved
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox084
Ox085
Ox086
Ox087
TIMERCNTL
TIMER
TIMERLSB
TIMERMSB
Read/Write Timer Control
Reserved
Read/Write Timer LSB
Read/Write Timer MSB
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox088
Ox089
8XMODE
REGA
Read/Write [1:0], Reserved [7:2]
Reserved
Bits 7-0 = 0x00
Bits 7-0 = 0x00
12