XR16M580 Datasheet, PDF (55/56 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M580
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
GENERAL DESCRIPTION................................................................................................ 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
FIGURE 1. XR16M580 BLOCK DIAGRAM .......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT FOR 32-PIN QFN AND 48-PIN TQFP PACKAGES IN 16 AND 68 MODE............................................. 2
FIGURE 3. PIN OUT ASSIGNMENT FOR 25-PIN BGA PACKAGE........................................................................................................... 3
ORDERING INFORMATION ............................................................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................ 4
1.0 PRODUCT DESCRIPTION ...................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 7
2.1 CPU INTERFACE ................................................................................................................................................ 7
FIGURE 4. XR16M580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ............................................................................ 7
2.2 SERIAL INTERFACE........................................................................................................................................... 8
FIGURE 5. XR16M580 TYPICAL SERIAL INTERFACE CONNECTIONS ................................................................................................... 8
FIGURE 6. XR16M580 TYPICAL SERIAL INTERFACE CONNECTIONS ................................................................................................... 9
2.3 DEVICE RESET ................................................................................................................................................. 10
2.4 INTERNAL REGISTERS.................................................................................................................................... 10
2.5 INT OUPUT ........................................................................................................................................................ 10
TABLE 1: INT PIN OPERATION FOR TRANSMITTER ........................................................................................................................... 10
TABLE 2: INT PIN OPERATION FOR RECEIVER ................................................................................................................................ 10
2.6 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT.............................................................................. 11
FIGURE 7. TYPICAL CRYSTAL CONNECTIONS .................................................................................................................................. 11
2.7 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR ........................................... 12
2.7.1 INDEPENDENT TX/RX BRG......................................................................................................................................... 12
FIGURE 8. BAUD RATE GENERATOR ............................................................................................................................................... 13
TABLE 3: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................... 13
2.8 TRANSMITTER.................................................................................................................................................. 14
2.8.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY........................................................................................... 14
2.8.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 14
FIGURE 9. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
2.8.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 15
FIGURE 10. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 15
2.9 RECEIVER ......................................................................................................................................................... 15
2.9.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 15
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 16
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 16
2.10 AUTO RTS (HARDWARE) FLOW CONTROL ................................................................................................ 17
2.11 AUTO RTS HYSTERESIS ............................................................................................................................... 17
TABLE 4: AUTO RTS (HARDWARE) FLOW CONTROL ........................................................................................................................ 17
2.12 AUTO CTS FLOW CONTROL......................................................................................................................... 17
FIGURE 13. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 18
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 19
TABLE 5: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 19
2.14 SPECIAL CHARACTER DETECT.................................................................................................................. 19
2.15 NORMAL MULTIDROP MODE........................................................................................................................ 19
2.15.1 AUTO ADDRESS DETECTION .................................................................................................................................. 20
2.16 INFRARED MODE ........................................................................................................................................... 20
FIGURE 14. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 21
2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWER-SAVE FEATURE ...................................................... 21
2.17.1 SLEEP MODE ............................................................................................................................................................. 21
2.17.2 POWER-SAVE FEATURE .......................................................................................................................................... 22
2.17.3 WAKE-UP INTERRUPT .............................................................................................................................................. 22
2.18 INTERNAL LOOPBACK................................................................................................................................. 23
FIGURE 15. INTERNAL LOOPBACK................................................................................................................................................... 23
3.0 UART INTERNAL REGISTERS............................................................................................................. 24
TABLE 6: UART INTERNAL REGISTERS .................................................................................................................................. 24
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ......................................... 25
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 26
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY .................................................................................. 26
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................... 26
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 26
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 27
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