XR16M580 Datasheet, PDF (26/56 Pages) Exar Corporation – 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO

XR16M580
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
TABLE 7: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
Baud Rate Generator Divisor
0 0 0 DREV RD
0 0 1 DVID RD
Bit-7
0
Bit-6
0
Bit-5
0
Bit-4
0
Bit-3
0
Bit-2
0
Bit-1
0
Bit-0
1
LCR[7] = 1
LCR≠0xBF
DLL= 0x00
DLM= 0x00
000
001
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
LCR[7] = 1
LCR≠0xBF
DLD[7:6]
010
DLD
RD/WR
BRG
select
Enable 4X Mode 8X Mode
Indepen-
dent
BRG
Bit-3
Bit-2
Bit-1
Bit-0
LCR[7] = 1
LCR≠0xBF
EFR[4] = 1
Enhanced Registers
000
FC
RD Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 FCTR RD/WR RX/TX Swap
0
select SCR
0
RS485 invert 0
0
interrupt RX IR
mode
010
EFR
RD/WR Auto
CTS#
Enable
Auto
RTS#
Enable
Special Enable
Char _{IER [7:4],}
Select _{ISR [5:4],}
FCR[5:3],
MCR[7:5],
DLD
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE”RECEIVER” ON PAGE 15.
4.2 Transmit Holding Register (THR) - Write-Only
SEE”TRANSMITTER” ON PAGE 14.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
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