XR16V794 Datasheet, PDF (53/53 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL

XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
3.1.2.2 TIMER [7:0] RESERVED....................................................................................................................................... 22
3.1.2.3 TIMERCNTL [7:0] REGISTER .............................................................................................................................. 22
TABLE 10: TIMER CONTROL COMMANDS ....................................................................................................................................... 22
TIMER OPERATION ................................................................................................................................................ 23
FIGURE 14. TIMER/COUNTER CIRCUIT............................................................................................................................................. 23
FIGURE 15. INTERRUPT OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES................................................................................. 23
3.1.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 24
3.1.4 REGA [7:0](DEFAULT 0X00) ....................................................................................................................................... 24
3.1.5 RESET [7:0] (DEFAULT 0X00)..................................................................................................................................... 24
3.1.6 SLEEP [7:0] ...................................................................................................................................... (DEFAULT 0X00) 24
3.1.7 DEVICE IDENTIFICATION AND REVISION................................................................................................................. 24
3.1.7.1 DVID [7:0] (DEFAULT 0X48) ................................................................................................................................. 25
3.1.7.2 DREV [7:0] (DEFAULT (0X01) .............................................................................................................................. 25
3.1.8 REGB [7:0] ....................................................................................................................................... (DEFAULT 0X00) 25
3.2 UART CHANNEL CONFIGURATION REGISTERS.......................................................................................... 26
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 26
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 27
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 28
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 28
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ............................................................................... 28
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 28
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. 30
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 30
4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 30
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 30
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 31
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 32
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 32
TABLE 15: PARITY PROGRAMMING ................................................................................................................................................. 33
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 34
4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 35
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 36
4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY.................................................................................... 37
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 37
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 38
4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................... 38
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 39
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 39
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 40
4.14 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 41
4.15 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 41
4.16 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 41
4.17 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY .................................................................. 41
4.18 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 41
4.19 XCHAR REGISTER, READ ONLY .................................................................................................................. 41
TABLE 19: UART RESET CONDITIONS ...................................................................................................................................... 42
ABSOLUTE MAXIMUM RATINGS ................................................................................. 43
ELECTRICAL CHARACTERISTICS............................................................................... 43
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 43
AC ELECTRICAL CHARACTERISTICS............................................................................................................. 44
FIGURE 16. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING ................................................................................................. 46
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING ........................................................................................ 47
FIGURE 18. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 48
FIGURE 19. RECEIVE INTERRUPT TIMING [NON-FIFO MODE]........................................................................................................... 48
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]......................................................................................................... 49
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]................................................................................................................... 49
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]................................................................................................................. 49
REVISION HISTORY ..................................................................................................................................... 51
TABLE OF CONTENTS ..................................................................................................... I
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