XR16V794 Datasheet, PDF (18/53 Pages) Exar Corporation – HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
2.16 Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at HIGH or mark condition while RTS# and DTR# are de-asserted (HIGH),
and CTS#, DSR# CD# and RI# inputs are ignored.
FIGURE 11. INTERNAL LOOP BACK
Transmit Shift Register
(THR/FIFO)
VCC
MCR bit-4=1
Receive Shift Register
(RHR/FIFO)
VCC
RTS#
CTS#
VCC
DTR#
DSR#
RI#
CD#
OP1#
OP2#
TX [3:0]
RX [3:0]
RTS# [3:0]
CTS# [3:0]
DTR# [3:0]
DSR# [3:0]
RI# [3:0]
CD# [3:0]
3.0 XR16V794 REGISTERS
The XR16V794 octal UART register set consists of the Device Configuration Registers that are accessible
directly from the data bus for programming general operating conditions of the UARTs and monitoring the
status of various functions. These functions include all 4 channel UART’s interrupt control and status, 16-bit
general purpose timer control and status, sleep mode, soft-reset, and device identification and revision. Also,
each UART channel has its own set of internal UART Configuration Registers for its own operation control,
status reporting and data transfer. These registers are mapped into a 256-byte of the data memory address
space. The following paragraphs describe all the registers in detail.
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