XR16L580_07 Datasheet, PDF (52/52 Pages) Exar Corporation – SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
xr
REV. 1.4.1
4.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 25
4.5 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
4.5.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.5.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
TABLE 7: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 27
4.6 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 27
TABLE 8: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION .............................................................................................. 28
4.7 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 28
TABLE 9: PARITY SELECTION .......................................................................................................................................................... 29
4.8 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30
4.9 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 31
4.10 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................. 32
4.11 SCRATCHPAD REGISTER (SPR) - READ/WRITE ..................................................................................... 33
4.12 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 33
4.13 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 33
4.14 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 33
4.15 ENHANCED FEATURE REGISTER (EFR) ................................................................................................. 33
TABLE 10: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 34
4.16 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - WRITE ONLY ................ 35
TABLE 11: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 36
ABSOLUTE MAXIMUM RATINGS...................................................................................37
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 37
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................37
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................38
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................39
Unless otherwise noted: TA=-40o to +85oC, Vcc=2.97 - 5.5V, 70 pF load where applicable ................................... 39
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................40
Unless otherwise noted: TA=-40o to +85oC, Vcc=1.62 - 2.75V, 70 pF load where applicable ................................. 40
FIGURE 15. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 16. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... 41
FIGURE 17. 16 MODE (INTEL) DATA BUS READ TIMING ................................................................................................................... 42
FIGURE 18. 16 MODE (INTEL) DATA BUS WRITE TIMING.................................................................................................................. 42
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 43
FIGURE 20. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 43
FIGURE 21. RECEIVE READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................... 44
FIGURE 22. TRANSMIT READY INTERRUPT TIMING [NON-FIFO MODE] ............................................................................................. 44
FIGURE 23. RECEIVE READY INTERRUPT TIMING [FIFO MODE] ....................................................................................................... 45
FIGURE 24. TRANSMIT READY INTERRUPT TIMING [FIFO MODE] ..................................................................................................... 45
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................46
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 MM)..............................................47
PACKAGE DIMENSIONS (28 PIN QFN - 5 X 5 X 0.9 MM)..............................................48
PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 MM)..............................................49
REVISION HISTORY.......................................................................................................................................50
TABLE OF CONTENTS ............................................................................................................ I
II