XR16L580_07 Datasheet, PDF (51/52 Pages) Exar Corporation – SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE

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REV. 1.4.1
XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES ..................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1
FIGURE 2. PACKAGES AND PIN OUT (24, 28 AND 32-PIN QFN PACKAGES)........................................................................................ 2
FIGURE 3. PACKAGES AND PIN OUT (48-TQFP PACKAGE)................................................................................................................ 3
ORDERING INFORMATION ................................................................................................................................ 3
PIN DESCRIPTIONS ......................................................................................................... 4
1.0 PRODUCT DESCRIPTION .................................................................................................................... 7
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 8
2.1 CPU INTERFACE ............................................................................................................................................. 8
FIGURE 4. XR16L580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ............................................................................. 8
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 9
2.3 DEVICE HARDWARE RESET .......................................................................................................................... 9
2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................... 9
2.5 INTERNAL REGISTERS ................................................................................................................................... 9
2.6 DMA MODE ...................................................................................................................................................... 9
2.7 INT (IRQ#) OUTPUT ......................................................................................................................................... 9
TABLE 1: INT (IRQ#) PIN OPERATION FOR TRANSMITTER ................................................................................................................. 9
TABLE 2: INT (IRQ#) PIN OPERATION FOR RECEIVER .................................................................................................................... 10
2.8 CRYSTAL OR EXTERNAL CLOCK INPUT ................................................................................................... 10
FIGURE 5. TYPICAL CRYSTAL CONNECTIONS ................................................................................................................................... 10
FIGURE 6. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 11
2.9 PROGRAMMABLE BAUD RATE GENERATOR .......................................................................................... 11
FIGURE 7. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 11
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 12
2.10 TRANSMITTER ............................................................................................................................................. 13
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 13
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 13
FIGURE 8. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 13
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 13
FIGURE 9. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.11 RECEIVER .................................................................................................................................................... 14
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 14
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................. 15
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 15
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................ 16
2.13 AUTO RTS HYSTERESIS ........................................................................................................................... 16
2.14 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
FIGURE 12. AUTO RTS AND CTS FLOW CONTROL OPERATION (NOT AVAILABLE IN 24-QFN PACKAGE)........................................... 17
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL .................................................................................. 18
TABLE 4: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.16 SPECIAL CHARACTER DETECT ............................................................................................................... 18
2.17 INFRARED MODE ........................................................................................................................................ 19
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 19
2.18 SLEEP MODE WITH WAKE-UP INTERRUPT AND POWER-SAVE FEATURE ........................................ 20
2.18.1 SLEEP MODE ........................................................................................................................................................... 20
2.18.2 POWER-SAVE FEATURE ........................................................................................................................................ 20
2.19 INTERNAL LOOPBACK .............................................................................................................................. 21
FIGURE 14. INTERNAL LOOP BACK ................................................................................................................................................. 21
3.0 UART INTERNAL REGISTERS ........................................................................................................... 22
TABLE 5: UART INTERNAL REGISTERS .................................................................................................................................... 22
TABLE 6: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1.......................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24
4.3 BAUD RATE GENERATOR DIVISORS (DLL AND DLM) - READ/WRITE ................................................... 24
4.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 24
4.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
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