XR16L2751_05 Datasheet, PDF (52/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
xr
REV. 1.2.2
4.0 INTERNAL Register descriptions ........................................................................................ 24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ........................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ......................................................................... 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ........................................................................... 24
4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 24
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation .................................................................... 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................ 26
4.4.1 Interrupt Generation: ................................................................................................................................ 26
4.4.2 Interrupt Clearing:..................................................................................................................................... 26
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ............................................................................................................................. 27
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ............................................................................... 27
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .................................................................................. 29
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ................................................................................. 29
TABLE 12: PARITY SELECTION................................................................................................................................................................ 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE ........ 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ..................................................................................... 32
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ............................................................................... 33
4.10 SCRATCHPAD REGISTER (SPR) - READ/WRITE ................................................................................. 34
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ................................................................................. 34
TABLE 13: SCRATCHPAD SWAP SELECTION............................................................................................................................................ 34
TABLE 14: AUTO RTS HYSTERESIS ....................................................................................................................................................... 35
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ................................................................................... 35
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE ............................................... 35
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................. 35
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ......................................................................... 36
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ............................................................................................. 36
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ............................................................................ 36
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .................................................................... 36
TABLE 15: TRIGGER TABLE SELECT ....................................................................................................................................................... 36
4.19 ENHANCED FEATURE REGISTER (EFR) ........................................................................................... 37
TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ............................................................................................................................... 37
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ............... 38
TABLE 17: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 39
ABSOLUTE MAXIMUM RATINGS...................................................................................40
ELECTRICAL CHARACTERISTICS ................................................................................40
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 40
DC ELECTRICAL CHARACTERISTICS ...........................................................................................................40
AC ELECTRICAL CHARACTERISTICS............................................................................................................41
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25 - 5.5V, 70 pF load
where applicable41
FIGURE 14. CLOCK TIMING .................................................................................................................................................................... 42
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B......................................................................................................... 43
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING .......................................................................................................................... 43
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING ......................................................................................................................... 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING.................................................................................................................. 44
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ................................................................. 45
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING ................................................................................................................ 45
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ............................................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B ............................................... 46
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B ................................................ 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ................................... 47
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B .................................... 48
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................49
REVISION HISTORY ....................................................................................................................................50
TABLE OF CONTENTS ................................................................................................................................. I
II