XR16L2751_05 Datasheet, PDF (23/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

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REV. 1.2.2
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
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TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
Stat. Int. Stat. Empty Data ^LCR[7]=0
CTS Int. RTS Int. Xoff Int. Sleep _{Enable Int.}
Int
Int.
Enable Enable Enable Mode
Enable Enable Enable
Enable
010
010
ISR
FCR
RD FIFOs FIFOs
0/
0/
INT
INT INT INT
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
LCR ≠ 0XBF
WR RXFIFO RXFIFO 0/
0/
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
DMA
Mode
Enable
TX
FIFO
Reset
RX FIFOs
FIFO Enable
Reset
011
LCR RD/WR Divisor Set TX Set Par- Even
Enable Break
ity
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
101
110
111
111
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal OP2#/INT Rsrvd
Lopback Output _(OP1#)
Enable Enable
RTS#
Output
Control
DTR#
Output
Control
LSR RD RX FIFO THR & THR
RX RX Fram- RX
RX
RX _{LCR ≠ 0XBF}
Global TSR Empty Break ing Error Parity Over- Data
Error Empty
Error run Ready
Error
MSR RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR ≠ 0xBF
FCTR[6]=0
EMSR WR
16X
Sam-
pling
Rate
Mode
LSR
Error
Inter-
rupt.
Imd/Dly#
Auto
RTS
Hyst.
bit-3
Auto
RTS
Hyst.
bit-2
Auto
RS485
Output
Inversion
Rsrvd
Rx/Tx
FIFO
Count
bit-1
Rx/Tx
FIFO
Count
bit-0
LCR ≠ 0XBF
FCTR[6]=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
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