XR16L2751_05 Datasheet, PDF (41/52 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

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REV. 1.2.2
XR16L2751
2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE
For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore
eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWERSAVE FEATURE” ON
PAGE 20.
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0^O TO 70^OC (-40^O TO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25 - 5.5V,
70 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
2.5
MIN
MAX
LIMITS
3.3
MIN
MAX
LIMITS
5.0
MIN
MAX
UNIT
-
Crystal Frequency
16
20
24 MHz
CLK External Clock Low/High Time
20
15
10
ns
OSC External Clock Frequency
24
33
50 MHz
T_AS
T_AH
T_CS
T_RD
T_DY
T_RDV
T_DD
T_WR
T_DY
T_DS
T_DH
T_ADS
T_ADH
T_RWS
T_RDA
T_RDH
T_WDS
T_WDH
T_RWH
Address Setup Time (16 Mode)
Address Hold Time (16 Mode)
Chip Select Width (16 Mode)
IOR# Strobe Width (16 Mode)
Read Cycle Delay (16 Mode)
Data Access Time (16 Mode)
Data Disable Time (16 Mode)
IOW# Strobe Width (16 Mode)
Write Cycle Delay (16 Mode)
Data Setup Time (16 Mode)
Data Hold Time (16 Mode)
Address Setup (68 Mode)
Address Hold (68 Mode)
R/W# Setup to CS# (68 Mode)
Read Data Access (68 mode)
Read Data Disable (68 mode)
Write Data Setup (68 mode)
Write Data Hold (68 Mode)
CS# De-asserted to R/W# De-asserted (68
Mode)
10
10
10
ns
10
10
10
ns
150
75
50
ns
150
75
50
ns
150
75
50
ns
135
70
45 ns
0
45
0
30
0
30 ns
150
75
50
ns
150
75
50
ns
25
20
15
ns
15
10
10
ns
10
10
10
ns
10
10
10
ns
10
10
10
ns
135
70
45 ns
45
30
30 ns
25
20
15
ns
15
10
10
ns
15
10
10
ns
T_CSL
T_CSD
CS# Width (68 Mode)
CS# Cycle Delay (68 Mode)
150
75
150
75
50
ns
50
ns
41