XR16C2850IJ-F Datasheet, PDF (51/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

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REV. 2.1.3
XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 25
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 25
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 26
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 27
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 28
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 29
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 30
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 31
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 32
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 32
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 32
TABLE 13: EXTENDED RTS HYSTERESIS ........................................................................................................................................ 33
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ......................................................................................... 33
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 33
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 33
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 33
4.16 TRIGGER LEVEL / FIFO DATA COUNT REGISTER (TRG) - WRITE-ONLY ............................................. 34
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ................................................................................. 34
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ....................................................................... 34
TABLE 14: TRIGGER TABLE SELECT ............................................................................................................................................... 34
4.19 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 35
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 35
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 36
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 37
ABSOLUTE MAXIMUM RATINGS .................................................................................. 38
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 38
ELECTRICAL CHARACTERISTICS................................................................................ 38
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 38
FIGURE 14. XR16C2850 VOL SINK CURRENT CHART ................................................................................................................... 39
FIGURE 15. XR16C2850 VOH SOURCE CURRENT CHART ............................................................................................................. 39
AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 40
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.90V TO 5.5V, 70 PF LOAD WHERE
APPLICABLE ................................................................................................................................................. 40
FIGURE 16. CLOCK TIMING............................................................................................................................................................. 41
FIGURE 17. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 41
FIGURE 19. DATA BUS WRITE TIMING ............................................................................................................................................ 42
FIGURE 18. DATA BUS READ TIMING .............................................................................................................................................. 42
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 43
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 43
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 44
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 44
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 45
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 45
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................ 46
PACKAGE DIMENSIONS (44 PIN PLCC) ....................................................................... 47
PACKAGE DIMENSIONS (40 PIN PDIP) ........................................................................ 48
REVISION HISTORY ...................................................................................................................................... 49
TABLE OF CONTENTS ............................................................................................................ I
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