XR16C2850IJ-F Datasheet, PDF (22/51 Pages) Exar Corporation – 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
xr
REV. 2.1.3
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS REG READ/
A2-A0 NAME WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
001
010
IER RD/WR 0/
0/
0/
0/
Modem RX Line TX
RX
CTS#
Int.
Enable
RTS#
Int.
Enable
Xoff Int..
Enable
Sleep
Mode
Enable
Status Int. Status- Empty Data
Enable Int.
Int.
Int.
Enable Enable Enable
ISR RD FIFOs FIFOs
0/
0/
INT
INT INT INT ^{LCR[7] = 0}
Enabled Enabled
INT
INT
Source Source
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
Bit-5 Bit-4
010
FCR
WR RXFIFO RXFIFO 0/
0/
DMA
TX
RX FIFOs
Trigger Trigger
TXFIFO TXFIFO
Trigger Trigger
Mode
Enable
FIFO FIFO Enable
Reset Reset
011
LCR RD/WR Divisor Set TX Set
Enable Break _Parity
Even
Parity
Parity
Enable
Stop
Bits
Word Word
Length Length
Bit-1 Bit-0
100
MCR RD/WR
0/
BRG
Pres-
caler
0/
IR Mode
ENable
0/
XonAny
Internal OP2#/INT Rsvd RTS# DTR#
Lopback Output _(OP1#) Output Output
Enable Enable
Control Control
1 0 1 LSR RD RX FIFO THR & THR
RX RX Fram- RX
RX
RX _{LCR[7] = 0}
Global TSR Empty Break ing Error Parity Over- Data
Error Empty
Error run Ready
Error
1 1 0 MSR RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta Delta Delta
RI# DSR# CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7] = 0
FCTR[6]=0
1 1 1 EMSR WR
Rsvd
Rsvd
Auto
RTS
Hyst.
bit-3
Auto
RTS
Hyst.
bit-2
Rsvd
Rsvd
Rx/Tx
FIFO
Count
Rx/Tx
FIFO
Count
LCR[7] = 0
FCTR[6]=1
1 1 1 FLVL RD Bit-7 Bit-6 Bit-5 Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
000
001
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0 LCR[7] = 1
Bit-0 ^{LCR ≠ 0xBF}
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