XR16L2551_07 Datasheet, PDF (48/49 Pages) Exar Corporation – LOW VOLTAGE DUART WITH POWERSAVE

XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
TABLE OF CONTENTS
REV. 1.1.3
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16L2551 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................8
2.1 CPU INTERFACE .............................................................................................................................................. 8
FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ........................................................................... 8
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 8
2.3 DEVICE RESET ................................................................................................................................................ 9
2.4 DEVICE IDENTIFICATION AND REVISION ..................................................................................................... 9
2.5 CHANNEL A AND B SELECTION .................................................................................................................... 9
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE ............................................................................................................................ 9
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE ............................................................................................................................ 9
2.6 DMA MODE ....................................................................................................................................................... 9
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE........................................................................................... 10
2.7 INTA AND INTB OUTPUTS ............................................................................................................................ 10
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 10
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 10
2.8 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 10
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 11
2.9 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 11
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 11
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE OPERATING SPEED12
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 13
2.10 TRANSMITTER ............................................................................................................................................. 13
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ....................................................................................... 13
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 13
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 14
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.11 RECEIVER .................................................................................................................................................... 14
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 15
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 15
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 15
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 16
2.13 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 17
2.14 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18
TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.15 SPECIAL CHARACTER DETECT ............................................................................................................... 18
2.16 INFRARED MODE ........................................................................................................................................ 19
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 19
2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWERSAVE FEATURE ................................................... 20
2.17.1 SLEEP MODE ........................................................................................................................................................... 20
2.17.2 POWERSAVE FEATURE.......................................................................................................................................... 20
2.18 INTERNAL LOOPBACK .............................................................................................................................. 21
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 21
3.0 UART INTERNAL REGISTERS ...........................................................................................................22
TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 22
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
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