XR16L2551_07 Datasheet, PDF (43/49 Pages) Exar Corporation – LOW VOLTAGE DUART WITH POWERSAVE

REV. 1.1.3
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
RX
INT
RXRDY#
Start
Bit
Stop
Bit
S D0:D7 S D0:D7 T
D0:D7 S D0:D7 T S D0:D7 T S D0:D7 T S D0:D7 T
T_SSI
RX FIFO drops
below RX
Trigger Level
RX FIFO fills up to RX
Trigger Level or RX Data
T_SSR
Timeout
FIFO
Empties
IOR#
(Reading data out
of RX FIFO)
T_RRI
T_RR
RXFIFODMA
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
TX FIFO
Empty
TX
(Unloading)
INT*
IER[1]
enabled
TXRDY#
Data in
TX FIFO
Start
Bit
Stop
Bit
S D0:D7 T
S D0:D7 T S D0:D7 T T S D0:D7 T S D0:D7 T
ISR is read
TX FIFO no
longer empty
Last Data Byte
Transmitted
S D0:D7 T
T_SRT
T_WRI
T_SI
TX FIFO
Empty
T_WT
IOW#
(Loading data
into FIFO)
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
TXDMA#
43