XR16L2551_07 Datasheet, PDF (10/49 Pages) Exar Corporation – LOW VOLTAGE DUART WITH POWERSAVE

XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
REV. 1.1.3
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the L2551 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see Figure 20 through Figure 25.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B 0 = 1 byte.
1 = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.7 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and Table 5 summarize the operating behavior for the transmitter and receiver. Also see Figure 20
through Figure 25.
INTA/B Pin
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
INTA/B Pin
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
2.8 Crystal Oscillator or External Clock Input
The L2551 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see “Programmable
Baud Rate Generator.”
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